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ISL6341, ISL6341A, ISL6341B
Data Sheet August 20, 2007 FN6538.0
5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
The ISL6341, ISL6341A, ISL6341B makes simple work out of implementing a complete control and protection scheme for a DC/DC stepdown converter driving N-Channel MOSFETs in a synchronous buck topology. Since it can work with either 5V or 12V supplies, this one IC can be used in a wide variety of applications within a system. The ISL6341, ISL6341A, ISL6341B integrates the control, gate drivers, output adjustment, monitoring and protection functions into a single 10 Ld Thin DFN package. The ISL6341, ISL6341A, ISL6341B provides single feedback loop, voltage-mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of 0.8% over temperature and line voltage variations. A fixed frequency oscillator (300kHz for ISL6341; 600kHz for ISL6341A, ISL6341B) reduces design complexity, while balancing typical application cost and efficiency. The PWM duty cycles range from 0% to around 85% at 300kHz (75% at 600kHz). The frequency, duty cycle and OCP are the only differences among the ISL6341, ISL6341A, ISL6341B. See Table 1 for a summary. Protection from overcurrent conditions is provided by monitoring the rDS(ON) of the lower MOSFET to inhibit PWM operation appropriately (the ISL6341, ISL6341B are slightly different from the ISL6341A; see "Overcurrent Protection (OCP)" on page 7 for details). This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. The output voltage is also monitored for undervoltage and overvoltage protection, in addition to monitoring for a PGOOD output.
Features
* Operates from +4.5V to 14.4V Supply Voltage (for bias) - 1.5V to 12V VIN Input Range (up to 20V is possible with restrictions; see "Input Voltage Considerations" on page 11) - 0.8V to ~VIN Output Range (duty cycle limited) - Integrated Gate Drivers; LGATE Uses VCC (5V to 12V); UGATE Uses External Boot Diode to 5V to 12V - 0.8V Internal Reference; 0.8% Tolerance * Simple Single-Loop Control Design - Traditional Dual Edge Modulator - Voltage-Mode PWM Control - Drives N-Channel MOSFETs * Fast Transient Response - High-Bandwidth Error Amplifier - 0% to 85% Max Duty Cycle for ISL6341 (75% for ISL6341A, ISL6341B) * Lossless, Programmable Overcurrent Protection - Uses Lower MOSFET's rDS(ON) * Output Voltage Monitoring - Undervoltage and Overvoltage Shutdown - PGOOD Output * Small Converter Size in 10 Ld 3x3 Thin DFN - 300kHz or 600kHz Fixed Frequency Oscillator - Fixed Internal Soft-Start, Capable into a Pre-biased Load - Enable/Shutdown Function on COMP/EN Pin * Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER PART TEMP. (Note) MARKING RANGE (C) ISL6341ACRZ* ISL6341BCRZ* ISL6341CRZ* ISL6341AIRZ* ISL6341BIRZ* ISL6341IRZ* 41AC 41BC 341C 41AI 41BI 6341 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-free) PKG. DWG. #
Applications
* Power Supplies for Microprocessors or Peripherals - PCs, Servers, Memory Supplies - DSP and Core Communications Processor Supplies * Subsystem Power Supplies - PCI, AGP; Graphics Cards; Digital TV - SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus Termination Supply * Cable Modems, Set-Top Boxes, and DSL Modems * Industrial Power Supplies; General Purpose Supplies * 5V or 12V-Input DC/DC Regulators * Low-Voltage Distributed Power Supplies; Point of Load
10 Ld 3x3 TDFN L10.3x3B 10 Ld 3x3 TDFN L10.3x3B 10 Ld 3x3 TDFN L10.3x3B 10 Ld 3x3 TDFN L10.3x3B 10 Ld 3x3 TDFN L10.3x3B 10 Ld 3x3 TDFN L10.3x3B
ISL6341EVAL1Z Evaluation Board *Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6341, ISL6341A, ISL6341B Pinout
ISL6341, ISL6341A, ISL6341B (10 LD 3x3 TDFN) TOP VIEW
BOOT PHASE UGATE LGATE GND 1 2 3 4 5 10 PGOOD 9 VOS 8 FB 7 COMP/EN 6 VCC
Block Diagram
VCC
SAMPLE AND HOLD 10A
OC COMPARATOR
+ -
POR AND SOFT-START
INTERNAL REGULATOR 5V INT. 20k
BOOT UGATE
PHASE
TO LGATE/OCSET
ERROR AMP 0.8V + -
PWM COMPARATOR + -
INHIBIT GATE CONTROL PWM LOGIC EN + +25% LGATE/OCSET OV1 GND UV1 OC + +10% OV2 PGOOD
VCC
FB
5V INT. 20A
0.7V
+
EN OSCILLATOR 300kHz OR 600kHz
-25% + -
COMP/EN
VOS -10% + UV2
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FN6538.0 August 20, 2007
ISL6341, ISL6341A, ISL6341B Typical Application
VCC 5V TO 12V
VIN 1.5V TO 12V VGD 5V TO 12V CBULK
CDCPL
CHF
VCC BOOT PGOOD 10 1 CBOOT TYPE II COMPENSATION PHASE 2 SHOWN COMP/EN ISL6341, 7 ISL6341A, 3 UGATE ISL6341B RF FB CI LGATE/OCSET 8 4 95 CF VOS GND R
OCSET
6
LOUT
+VO
COUT
ROFFSET
RS
RVOS1
RVOS2
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ISL6341, ISL6341A, ISL6341B
Absolute Maximum Ratings
Supply Voltage, (VCC) . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . GND - 0.3V to 36V BOOT to PHASE Voltage (VBOOT - VPHASE) . . . GND - 0.3V to 15V -0.3V to 16V (<10ns, 10J) UGATE Voltage (VUGATE) . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V VPHASE - 3.5V (<100ns Pulse Width, 2J) to VBOOT +0.3V LGATE/OCSET Voltage (VLGATE) . . . . . . GND - 0.3V to VCC + 0.3V GND - 5V (<100ns Pulse Width, 2J) to VCC + 0.3V PHASE Voltage (VPHASE) . . . . . . . . . .GND - 0.3V to VBOOT + 0.3V GND - 8V (<400ns, 20J) to 30V (<200ns, VBOOT-GND <36V) FB, VOS, COMP/EN Voltage . . . . . . . . . . . . . . . . . GND - 0.3V to 6V PGOOD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld TDFN Package (Notes 1, 2). . . . 44 3.5 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . +4.5V to 14.4V Ambient Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air, with "direct attach" features. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. Limits should be considered typical and are not production tested. 4. Limits established by characterization and are not production tested.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Input Bias Supply Current Input Bias Supply Current POWER-ON RESET Rising VCC POR Threshold VCC POR Threshold Hysteresis OSCILLATOR Switching Frequency
Test Conditions: VCC = 12V, TJ = 0 to +85C, Unless Otherwise Noted. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC_dis IVCC_en VPOR
VCC = 12V; disabled VCC = 12V; enabled (but not switching) 6.4
7.0 8.9 10.4
mA mA
3.8 0.15
4.2 0.48
4.47 0.85
V V
fOSC
ISL6341C ISL6341I ISL6341AC, ISL6341BC ISL6341AI, ISL6341BI
270 240 540 510
300 300 600 600 1.5
330 330 660 660
kHz kHz kHz kHz VP-P
Ramp Amplitude (Note 3) REFERENCE Reference Voltage Tolerance
VOSC VREF ISL6341C, ISL6341AC, ISL6341BC ISL6341I, ISL6341AI, ISL6341BI 0.7936 0.7920
0.8000 0.8000
0.8064 0.8080
V V
ERROR AMPLIFIER DC Gain (Note 3) Gain-Bandwidth Product (Note 3) Slew Rate (Note 3) GATE DRIVERS Upper Gate Source Impedance Upper Gate Sink Impedance Lower Gate Source Impedance Lower Gate Sink Impedance Upper Gate Source Impedance RUG-SRCh VCC = 12V; I = 50mA RUG-SNKh VCC = 12V; I = 50mA RLG-SRCh VCC = 12V; I = 50mA RLG-SNKh VCC = 12V; I = 50mA RUG-SRCl VCC = 5V; I = 50mA 2.1 1.6 1.4 1.0 2.4 GAIN GBWP SR 96 20 8 dB MHz V/s
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Electrical Specifications
PARAMETER Upper Gate Sink Impedance Lower Gate Source Impedance Lower Gate Sink Impedance PROTECTION/DISABLE OCSET Current Source Enable Threshold (COMP/EN pin) VOS Rising Trip (PGOOD OV; +10%) VOS Rising Trip (PGOOD OV) hysteresis VOS Falling Trip (PGOOD UV; -10%) VOS Falling Trip (PGOOD UV) hysteresis VOS Rising Threshold (OV; +25%) VOS Falling Threshold (UV; -25%) VOS Threshold (OV; 50% of VOUT) VOS Bias Current PGOOD VOS = 0.25V IPGOOD = 4mA 0.980 0.580 0.380 -1500 0.10 0.708 IOCSET VENABLE LGATE/OCSET = 0V 9 0.683 0.868 10 0.700 0.880 16 0.720 16 1.000 0.600 0.400 -250 0.18 1.020 0.620 0.410 -100 0.30 0.732 11 0.717 0.888 A V V mV V mV V V V nA V Test Conditions: VCC = 12V, TJ = 0 to +85C, Unless Otherwise Noted. (Continued) SYMBOL TEST CONDITIONS MIN TYP 1.7 1.5 1.1 MAX UNITS RUG-SNKl VCC = 5V; I = 50mA RLG-SRCl RLG-SNKl VCC = 5V; I = 50mA VCC = 5V; I = 50mA
Functional Pin Description
VCC (Pin 6)
This pin provides the bias supply for the ISL6341, ISL6341A, ISL6341B, as well as the lower MOSFET's gate. An internal regulator will supply bias as VCC rises above 5V, but the LGATE/OCSET will still be sourced by VCC. Connect a well-decoupled 5V to 12V supply to this pin.
UGATE driver, and to monitor the voltage drop across the lower MOSFET for overcurrent protection. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off.
UGATE (Pin 3)
Connect this pin to the gate of upper MOSFET; it provides the PWM-controlled gate drive. It is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off.
FB (Pin 8)
This pin is the inverting input of the internal error amplifier. Use FB, in combination with the COMP/EN pin, to compensate the voltage-control feedback loop of the converter. A resistor divider from VOUT to FB to GND is used to set the regulation voltage.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive an N-Channel MOSFET (equal to VGD minus the BOOT diode voltage drop), with respect to PHASE.
VOS (Pin 9)
This input pin monitors the regulator output for OV and UV protection, and PGOOD (OV and UV). Connect a resistor divider from VOUT to VOS to GND, with the same ratio as the FB resistor divider. It is usually not recommended to share one divider for both FB and VOS; the response to a fault may not be as quick or robust. There is a small pull-up bias current on the pin; if the VOS pin is not connected, the OV protection would be tripped to protect the load.
COMP/EN (Pin 7)
This is a multiplexed pin. During soft-start and normal converter operation, this pin represents the output of the error amplifier. Use COMP/EN, in combination with the FB pin, to compensate the voltage-control feedback loop of the converter. Pulling COMP/EN low (VENABLE = 0.7V nominal) will disable the controller, which causes the oscillator to stop, the LGATE and UGATE outputs to be held low, and the soft-start circuitry to re-arm. The external pull-down device will initially need to overcome up to 5mA of COMP/EN output current. However, once the IC is disabled, the COMP output will also be disabled, so only a 20A current source will continue to draw current. When the pull-down device is released, the COMP/EN pin will start to rise, at a rate determined by the 20A charging up the capacitance on the COMP/EN pin. When the COMP/EN pin rises above the VENABLE trip point, the ISL6341, ISL6341A, ISL6341B will begin a new initialization and soft-start cycle.
GND (Pin 5)
This pin represents the signal and power ground for the IC. This pin is the high current connection, and should be tied to the ground island/plane through the lowest impedance connection available. The metal pad under the package should also be connected to the GND plane for thermal conductivity, but does not conduct any current.
PHASE (Pin 2)
Connect this pin to the source of the upper MOSFET, and the drain of the lower MOSFET. It is used as the sink for the
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LGATE/OCSET (Pin 4)
Connect this pin to the gate of the lower MOSFET; it provides the PWM-controlled gate drive (from VCC). This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. During a short period of time following Power-On Reset (POR) or shut-down release, this pin is also used to determine the overcurrent threshold of the converter. Connect a resistor (ROCSET) from this pin to GND. See "Overcurrent Protection (OCP)" on page 7 for equations. An overcurrent trip latches off the output, requiring cycling VCC off and on, or by toggling COMP/EN. Some of the text describing the LGATE function may leave off the OCSET part of the name when it is not relevant to the discussion.
VCC (2V/DIV)
~4.3V POR VOUT (1V/DIV) COMP/EN (1V/DIV)
GND>
PGOOD (Pin 10)
This output is an open-drain pull-down device that reflects the state of the PGOOD comparators. An external pull-up resistor should be connected to a supply 6V. The output will be held low through the soft-start ramp, and is allowed to go high at the end of soft-start, if the VOS voltage is within its window. The PGOOD window is tighter than the OV or UV protection window, so it may give an early warning of a problem. The PGOOD does respond directly to an OCP condition, but may also go low if VOUT drops low enough before an OCP trip.
FIGURE 1. POR AND SOFT-START OPERATION
Figure 2 shows a typical power-up sequence in more detail. The initialization starts at t0, when either VCC rises above VPOR, or the COMP/EN pin is released (after POR). The COMP/EN will be pulled up by an internal 20A current source, but the timing will not begin until the COMP/EN exceeds the VENABLE trip point (at t1). The external capacitance of the disabling device, as well as the compensation capacitors, will determine how quickly the 20A current source will charge the COMP/EN pin. With typical values, it should add a small delay compared to the soft-start times. The COMP/EN will continue to ramp to ~1V.
LGATE STARTS SWITCHING COMP/EN (0.25V/DIV) VOUT (0.25V/DIV) PGOOD (2V/DIV) LGATE/OCSET 0.25V/DIV
Functional Description
TABLE 1. SUMMARY OF FEATURE DIFFERENCES PART NUMBER ISL6341 MAX DUTY CYCLE 85% 75% 75% OCP (OVERCURRENT PROTECTION) Latch off; toggle POR or COMP/EN to restart "Hiccup" mode (infinite retries) Latch off; toggle POR or COMP/EN to restart
GND>
fSW 300kHz
0.7V
ISL6341A 600kHz ISL6341B 600kHz
Initialization (POR and OCP sampling)
Figure 1 shows a simplified timing diagram. The Power-OnReset (POR) function continually monitors the bias voltage at the VCC pin. Once the rising POR threshold is exceeded (VPOR = 4.3V nominal), the POR function initiates the Overcurrent Protection (OCP) sample and hold operation (while COMP/EN is ~1V). When the sampling is complete, VOUT begins the soft-start ramp. If the COMP/EN pin is held low during power-up, that will just delay the initialization until it is released and the COMP/EN voltage is above the VENABLE trip point.
t0 t1 t2 t3 t4
4.0ms
0.8ms
4.0ms
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION
From t1, there is a nominal 4ms delay, which allows the VCC pin to rise. At the same time, the LGATE/OCSET pin is initialized by disabling the LGATE driver and drawing IOCSET (nominal 10A) through ROCSET. This sets up a voltage that will represent the OCSET trip point for the OCP sample and hold operation. The sample and hold uses a digital counter and DAC (to save the voltage so the stored value does not degrade) for as long as the VCC is above VPOR. See "Overcurrent Protection (OCP)" on page 7 for more details on the equations and variables. Upon the completion of sample and hold at t2, the soft-start operation is initiated (around 0.8ms delay to t3),
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and then around 4ms for the output voltage to ramp up (0% to 100%) between t3 and t4. The PGOOD output is allowed to go high at t4 if VOS (and thus VOUT) is within the PGOOD window.
VOUT OVER-CHARGED
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on the non-inverting terminal of the error amp from zero to 0.8V in a nominal 4ms. The output voltage will thus follow the ramp, from zero to final value, in the same 4ms. The ramp is created digitally, so there will be small discrete steps. There is no simple way to change this ramp rate externally, as it is fixed by the 300kHz (or 600kHz) switching frequency (and the ramp and delay time is the same for both frequencies). After an initialization period (t2 to t3), the error amplifier (COMP/EN pin) is enabled, and begins to regulate the converter's output voltage during soft-start. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitors. When the internally generated soft-start voltage exceeds the reference voltage (0.8V), the softstart is complete, and the output should be in regulation at the expected voltage. This method provides a rapid and controlled output voltage rise; there is no large in-rush current charging the output capacitors. The entire start-up sequence from POR typically takes 9ms; 5ms for the delay and OCP sample, and 4ms for the soft-start ramp. Figure 3 shows the normal VOUT curve in blue; initialization begins at t0, and the output ramps between t1 and t2. If the output is pre-biased to a voltage less than the expected value (as shown by the magenta curve), the ISL6341, ISL6341A, ISL6341B will detect that condition. Neither MOSFET will turn-on until the soft-start ramp voltage exceeds the output; VOUT starts seamlessly ramping from there. There is a restriction for the pre-bias case; if the pre-biased VOUT is greater than VGD, then the boot cap may get discharged, and will not be able to restart. For example, if VIN = 12V, VOUT = 8V and prebiased to 6V, and VGD is only 5V, then the voltage left on the boot cap (to UGATE) will not be able to turn on the upper FET. The simple solution here is to use the 12V for VGD. The guideline is to make VGD diode - Vth upper FET > VOUT to prevent this condition. If the output is pre-biased to a voltage above the expected value (as in the red curve), neither MOSFET will turn-on until the end of the soft-start, at which time it will pull the output voltage quickly down to the final value. Any resistive load connected to the output will help pull-down the voltage (at the RC rate of the R of the load and the C of the output capacitance). One exception to the over-charged case is if the pre-bias is high enough to trip OV protection (>1V on VOS); then LGATE will pulse to try to pull VOUT lower. The IC will remain latched in this mode until VCC power is toggled. 7
VOUT PRE-BIASED
GND>
VOUT NORMAL
t0
t1
t2
FIGURE 3. SOFT-START WITH PRE-BIAS
If the VIN to the upper MOSFET drain (or the VGD voltage to the boot diode) is from a different supply that comes up after VCC, the soft-start would start its cycle, but with no output voltage ramp. Once the undervoltage protection is enabled (at the end of the soft-start ramp), the output will latch off. Therefore, for normal operation, VIN (and VGD) must be high enough before or with VCC. If this is not possible, then the alternative is add sequencing logic to the COMP/EN pin to delay the soft-start until the VIN (and VGD) supply is ready (see "Input Voltage Considerations" on page 11). If the IC is disabled after soft-start (by pulling COMP/EN pin low), and then enabled (by releasing the COMP/EN pin), then the full initialization (including a new OCP sample) will take place. If the output is shorted to GND during soft-start, the OCP will handle it, as described in the next section.
Overcurrent Protection (OCP)
The overcurrent function protects the converter from a shorted output by using the lower MOSFET's ON-resistance, rDS(ON), to monitor the current. A resistor (ROCSET) programs the overcurrent trip level (see "Typical Application" diagram on page 3). This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. Following POR and release of COMP/EN, the ISL6341, ISL6341A, ISL6341B initiates the Overcurrent Protection sample and hold operation. The LGATE driver is disabled to allow an internal 10A current source to develop a voltage across ROCSET. The ISL6341, ISL6341A, ISL6341B samples this voltage (which is referenced to the GND pin) at the LGATE/OCSET pin, and holds it in a counter and DAC combination. This sampled voltage is held internally as the Overcurrent Set Point, for as long as power is applied, or until a new sample is taken after coming out of a COMP/EN shut-down.
FN6538.0 August 20, 2007
ISL6341, ISL6341A, ISL6341B
The actual monitoring of the lower MOSFET's ON-resistance starts 200ns (nominal) after the edge of the internal PWM logic signal (that creates the rising external LGATE signal). This is done to allow the gate transition noise and ringing on the PHASE pin to settle out before monitoring. The monitoring ends when the internal PWM edge (and thus LGATE) goes low. The OCP can be detected anywhere within the above window. To allow sufficient time to detect OCP, the regulator will limit the maximum UGATE duty cycle to ~85% at 300kHz (~75% at 600kHz); there will always be an LGATE pulse of at least 300ns. This minimum width will also act as a boot-refresh function. If the boot capacitor loses any charge while UGATE is high, it will be refreshed each cycle while LGATE is high. The ISL6341, ISL6341B and ISL6341A share most of the detection circuitry; the main difference between them is what happens after detection. ISL6341, ISL6341B When overcurrent is detected (while LGATE is high), the logic will disable UGATE, and leave LGATE high until the current drops to 1/2 of its programmed OCP value. This may take several clock cycles, and it keeps the current from building up too high. Once the current is low enough, UGATE will go high on the next PWM cycle, and OCP will be monitored when LGATE goes high. If OCP trips a 2nd time, it will again wait until the current drops. If it trips again the 3rd time, it will latch off the output (LGATE and UGATE low). If there is no OCP trip on one of the retries, then the trip-counter resets to zero, and three new consecutive cycles are required to latch off.
IINDUCTOR (10A/DIV) GND>
As the output inductor current rises and falls, the output voltage is also affected. Note that in extreme cases during the three consecutive trips, the UV may actually trip before the OCP. The IC provides protection in either case, but perhaps not quite at the programmed current. An OCP trip can be reset by toggling either POR or COMP/EN, but a UV trip is only reset by toggling POR. See Table 2 for the protection summary. Starting up into a shorted load will be handled the same way; but the waveforms may look different, since the output is not yet at its final value. OCP is always enabled during soft-start (UV is not); it will need the three consecutive trips to latch off. ISL6341A Figure 5 shows the same conditions for the ISL6341A. For this version, when overcurrent is first detected (while LGATE is high), the logic will shut off the output (LGATE and UGATE both go low), and the current goes to zero.
IINDUCTOR (10A/DIV)
OC
0A> LGATE (12V/DIV)
GND> UGATE (24V/DIV)
FIGURE 5. OCP TIMING (ISL6341A ONLY)
OC 1/2 OC 0A> LGATE (12V/DIV)
It will then go into a "hiccup" mode of infinite retries. After two dummy soft-start time-outs, a real soft-start will begin. If the short is still there, it will trip during the soft-start ramp, and will start another retry cycle. Once the short is removed, the next real soft-start will be successful, and normal operation can continue. Figure 6 shows the ISL6341A output response during a retry of an output shorted to GND. At time t0, the output has been turned off, due to sensing an overcurrent condition. There are two internal soft-start delay cycles (t1 and t2) to allow the MOSFETs to cool down, to keep the average power dissipation in retry at an acceptable level. At time t2, the output starts a normal soft-start cycle, and the output tries to ramp. If the short is still applied, and the current reaches the OCSET trip point any time during soft-start ramp period, the output will shut off and return to time t0 for another delay cycle. The retry period is thus two dummy soft-start cycles plus one variable one, which depends on how long it takes to trip the sensor each time. Figure 6 shows an example where the output gets about half-way up before shutting down; therefore, the retry (or hiccup) time will be around 12ms. The
GND> UGATE (24V/DIV)
GND>
FIGURE 4. OCP TIMING (ISL6341, ISL6341B ONLY)
Figure 4 shows a typical waveform for the ISL6341, ISL6341B, where the normal inductor current is around 10A, and the OCP trip is 16A. This is just an illustration; the actual shape of the waveforms depends on the component values, as well as the characteristics of the load and the short. On the third trip, the gate drivers stop switching, and the current goes to zero. To recover from this latched off condition, the user must toggle VCC (power-down and up) for a new POR, or toggle COMP/EN pin to restart (either includes initialization and soft-start).
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minimum should be nominally 9.6ms and the maximum 14.4ms. If the short condition is finally removed, the output should ramp up normally on the next t2 cycle. Starting up into a shorted load looks the same as a retry into that same shorted load. In both cases, OCP is always enabled during soft-start; once it trips, it will go into retry (hiccup) mode. The retry cycle will always have two dummy time-outs, plus whatever fraction of the real soft-start time passes before the detection and shut-off; at that point, the logic immediately starts a new two dummy cycle time-out. MOSFETs for the ISL6341, ISL6341A, ISL6341B are not expected to handle the power of the maximum trip point. Any voltage setting above 600mV will clamp to the maximum setting. No resistor at all should give the clamped maximum value (unless the loading on the LGATE prevents charging the node fully). However, a resistor (>60k) is recommended; there is no low-voltage clamp on LGATE, so it could rise to over 3V and turn-on for 4ms during the sampling; that could discharge a pre-biased output. There is no way to disable the OCP, but setting it to the maximum value may be far enough above the normal expected range. Note that conditions during power-up may look different than normal operation. For example, during power-up in a 12V system, the IC starts operation just above 4V; if the supply ramp is slow, the soft-start ramp might be over well before 12V is reached. So with lower gate drive voltages, the rDS(ON) of the MOSFETs will be higher during power-up, effectively lowering the OCP trip. In addition, the ripple current will likely be different at lower input voltage. Another factor is the digital nature of the soft-start ramp. On each discrete voltage step, there is in effect a small load transient and a current spike to charge the output capacitors. The height of the current spike is not controlled; it is affected by the step size of the output, the value of the output capacitors, as well as the IC error amp compensation. So it is possible to trip the overcurrent with in-rush current, in addition to the normal load and ripple considerations. OCP is always enabled during soft-start, so there is protection starting up into a shorted load.
INTERNAL SOFT-START RAMP
VOUT (0.5V/DIV)
GND> 4.8ms t0 t1 4.8ms 0ms TO 4.8ms t2 t0 4.8ms
FIGURE 6. OCP RETRY OPERATION (ISL6341A ONLY)
OVERCURRENT EQUATIONS For both the ISL6341, ISL6341B and ISL6341A, the overcurrent function will trip at a peak inductor current (IPEAK) determined by Equation 1:
I OCSET xR OCSET I PEAK = ------------------------------------------------r DS ( ON ) (EQ. 1)
Undervoltage Protection
The output is protected against undervoltage conditions by monitoring the VOS pin. An external resistor divider (similar ratio to the one on the FB pin) makes the voltage equal the 0.8V internal reference under normal operation. If the output goes too low (25% below 0.8V = 0.6V nominal on VOS), the output will latch off, with UGATE and LGATE both forced low. This requires toggling VCC (power-down and up) to restart (toggling COMP/EN will NOT restart it). The UV protection is not enabled until the end of the soft-start ramp (as shown in Figure 2). Figure 7 shows a case where VOUT (and thus VOS) is pulled down to the 75% point; both gate drivers stop switching, and the VOUT is pulled low by the disturbance, as well as the load, at a rate determine by the conditions, and the output components.
where IOCSET is the internal OCSET current source (10A typical). The OC trip point varies in a system mainly due to the MOSFET's rDS(ON) variations (over process, current and temperature). To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from Equation 1 with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for I PEAK > I OUT ( MAX ) + ---------- , 2 where I is the output inductor ripple current. For an equation for the ripple current see "Output Inductor Selection" on page 14. The range of allowable voltages detected (IOCSET*ROCSET) is 0mV to 550mV; but the practical range for typical MOSFETs is smaller. If the voltage drop across ROCSET is set too low, that can cause almost continuous OCP tripping and latch-off. It would also be very sensitive to system noise and in-rush current spikes, so it should be avoided. The maximum setting is 550mV, but most of the recommended 9
( I )
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than the protection, in order to give an early warning to a possible problem. The response time of the comparators should be less than 1s; the separate VOS input is not slowed down by the compensation on the FB pin. If a fast or robust response is not required, it may be possible to connect the VOS pin to the FB pin, in order to share the resistor divider. If the VOS pin is accidentally disconnected, a small bias current on-chip will force an overvoltage condition. Figure 9 shows how the PGOOD output responds to a ramp that trips in each direction (without reaching either protection trip point at 25%); PGOOD is valid (high) as long as VOUT (and thus VOS) is within the 10% window.
110%
75%
VOUT (0.25V/DIV)
GND> LGATE (12V/DIV)
GND> UGATE (24V/DIV)
GND>
FIGURE 7. UNDERVOLTAGE PROTECTION
90%
Overvoltage Protection
The output is protected against overvoltage conditions by monitoring the VOS pin, similar to undervoltage. If the output goes too high (25% above 0.8V = 1.0V nominal on VOS), the output will latch off. As shown in Figure 8, UGATE will be forced low, but LGATE will be forced high (to try to pull-down the output) until the output drops to 1/2 of the normal voltage (50% of 0.8V = 0.4V nominal on VOS). Overvoltage latch-off requires toggling VCC (power-down and up) to restart (toggling COMP/EN will NOT restart it). The OV protection is not enabled until the rising VCC POR trip point is exceeded. If the VOS pin is disconnected, a small bias current on-chip will force an overvoltage condition.
VOUT (0.5V/DIV) 125%
VOUT (0.25V/DIV)
GND> PGOOD (2V/DIV)
GND>
FIGURE 9. PGOOD UNDERVOLTAGE AND OVERVOLTAGE
The PGOOD output is an open-drain pull-down NMOS device; it can deliver 4.0mA of sink current at 0.3V when power is NOT GOOD. A pull-up resistor to an external supply voltage sets the high level voltage when power is GOOD. The supply should be 6.0V, and is usually the one that powers the logic monitoring the PGOOD output. If PGOOD function is not used, the PGOOD pin can be left floating. The PGOOD pin will be held low once VCC is above the rising POR trip point, and during soft-start (but if the PGOOD supply is up before or with VCC, it may be pulled high initially until the logic has enough voltage to turn on the output). Once the soft-start ramp is done (VOUT, VOS and FB should each be at 100% of their final value), the PGOOD pin will be allowed to go high, if the output voltage is within the expected window. There is no additional delay after soft-start is done. Note that the overcurrent protection does directly affect the PGOOD output, before the output voltage monitoring would sense when VOUT drops 10%. The overvoltage and undervoltage protection circuits don't directly effect PGOOD, but since the PGOOD UV and OV windows are tighter, the PGOOD output should already be low by the time either protection is tripped.
50% GND> LGATE (12V/DIV)
GND> UGATE (24V/DIV)
GND>
FIGURE 8. OVERVOLTAGE PROTECTION
PGOOD
The PGOOD function output monitors the output voltage using the same VOS pin and resistor divider of the undervoltage and overvoltage protection, but with separate comparators for each. The rising OV trip point (10% above 0.8V = 0.88V nominal on VOS) and the falling UV trip point (10% below 0.8V = 0.72V nominal on VOS) will trip sooner
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TABLE 2. PROTECTION SUMMARY PROTECTION ACTION TAKEN ENABLED AFTER RESET BY
OCP (41/41B) VOUT latches off; LGATE and UGATE low. OCP (41A) UVP (-25%) OVP (+25%)
POR or POR or COMP/EN COMP/EN
The VOS pin is expected to see the same ratio for its resistor divider; RVOS1 should also be chosen in the 1k to 5k (1% for accuracy) range. To simplify the BOM, RVOS1 should match RS, and RVOS2 should match ROFFSET.
Input Voltage Considerations
The "Typical Application" diagram on page 3 shows a standard configuration where VCC is 5V to 12V, which includes the standard 5V (10%) or 12V (20%) power supply ranges. The gate drivers use the VCC voltage for LGATE, and VGD (also 5V to 12V) for BOOT/UGATE. There is an internal 5V regulator for bias. The VIN to the upper MOSFET can share the same supply as VCC, but can also run off a separate supply or other sources, such as outputs of other regulators. If VCC powers up first, and the VIN or VGD are not present by the time the initialization is done, then undervoltage will trip at the end of soft-start (and will not recover without toggling VCC; toggling COMP/EN will not restart it). Therefore, either the supplies must be turned on in the proper order (together, or VCC last), or the COMP/EN pin should be used to disable VOUT until all supplies are ready. Figure 10 shows a simple sequencer for this situation. If VCC powers up first, Q1 will be off and R3 pulling to VCC will turn Q2 on, keeping the ISL6341, ISL6341A, ISL6341B in shut-down. When VIN turns on, the resistor divider R1 and R2 determines when Q1 turns on, which will turn off Q2, and release the shut-down. If VIN powers up first, Q1 will be on, turning Q2 off; so the ISL6341, ISL6341A, ISL6341B will start-up as soon as VCC comes up. The VENABLE trip point is 0.7V nominal, so a wide variety of NFET's or NPN's or even some logic IC's can be used as Q1 or Q2; but Q2 must be low leakage when off (open-drain or open-collector) so as not to interfere with the COMP output. Q2 should also be placed near the COMP/EN pin.
VIN VCC R3 to COMP/EN
Infinite retries; wait ~10ms, POR or Not and try a new Soft-Start ramp. COMP/EN Applicable VOUT latches off; LGATE and UGATE low. after SS ramp POR POR
POR VOUT latches off; UGATE low; LGATE goes low and high to keep VOUT within 50% and 125% of nominal. VOS pin open will trigger OV. PGOOD goes low if VOS is 10% too low. PGOOD goes low if VOS is 10% too high. after SS ramp after SS ramp
PGOOD (UV; -10%) PGOOD (OV; +10%) PGOOD (OCP)
POR or COMP/EN POR or COMP/EN POR or COMP/EN or good SS ramp
PGOOD goes low if OCP trips after SS ramp
Switching Frequency
The switching frequency is a fixed 300kHz for the ISL6341, and 600kHz for the ISL6341A, ISL6341B. It cannot be adjusted externally, and the various soft-start delays and ramps are fixed at the same times for either frequency.
Output Voltage Selection
The output voltage can be programmed to any level between the 0.8V internal reference, up to the VIN supply, with the 85% duty cycle restriction for the ISL6341 (75% for the ISL6341A, ISL6341B). Additional duty cycle margin due to the rDS(ON) drop across the upper FET at maximum load needs to be factored in as well. An external resistor divider is used to scale the output voltage relative to the internal reference voltage, and feed it back to the inverting input of the error amp. See the "Typical Application" schematic on page 3 for more detail; RS is the upper resistor; ROFFSET (shortened to RO below) is the lower one. The recommended value for RS is 1k to 5k (1% for accuracy) and then ROFFSET is chosen according to Equation 2. Since RS is part of the compensation circuit (see "Feedback Compensation" on page 12), it is often easier to change ROFFSET to change the output voltage; that way the compensation calculations do not need to be repeated. If VOUT = 0.8V, then ROFFSET can be left open. Output voltages less than 0.8V are not available.
( RS + RO ) V OUT = 0.8V * --------------------------RO R S * 0.8V R O = ---------------------------------V OUT - 0.8V
R1
R2
Q1
Q2
FIGURE 10. SEQUENCER CIRCUIT
The VIN range can be as low as ~1.5V (for VOUT as low as the 0.8V reference). It can be as high as 20V (for VOUT just below VIN, limited by the maximum duty cycle). There are some restrictions for running high VIN voltage. The first consideration for high VIN is the maximum BOOT voltage of 36V. The VIN (as seen on PHASE) plus VGD (boot voltage - minus the diode drop), plus any ringing (or other transients) on the BOOT pin must be less than 36V. If VIN is 20V, that limits VGD plus ringing to 16V.
(EQ. 2)
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The second consideration is the maximum voltage ratings for VCC and BOOT-PHASE (for VGD); both are set at 15V. If VIN is above the maximum operating range for VCC of 14.4V, then both VCC and VGD need to be supplied separately. They can be derived from VIN (using a linear regulator or equivalent), or they can be independent. In either case, they must satisfy the power supply sequencing requirements noted earlier (either power-up in the proper order, or use a sequencer to disable the output until they are all ready). The third consideration for high VIN is duty cycle. Very low duty cycles (such as 20V in to 1.0V out, for 5% duty cycle) require component selection compatible with that choice (such as low rDS(ON) lower MOSFET, a good LC output filter, and compensation values to match). At the other extreme (for example, 20V in to 12V out), the upper MOSFET needs to be lower rDS(ON). There is also the maximum duty cycle restriction. In all cases, the input and output capacitors and both MOSFETs must be rated for the voltages present.
+VGD VOUT VOS COMP/EN FB +VCC VCC CVCC GND BOOT CBOOT +VIN Q1 LO VOUT LOAD
ISL6341, ISL6341A, ISL6341B
PHASE LGATE/OCSET Q2 CO
ROCSET
FIGURE 12. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding.
ISL6341, ISL6341A, ISL6341B UGATE PHASE Q2 VIN
Figure 12 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. Locate the resistor, ROSCET close to the LGATE/OCSET pin because the internal current source is only 10A. Minimize any leakage current paths on the COMP/EN pin. All components used for feedback compensation and VOS resistor divider (inside the dotted box) should be located as close to the IC as practical. Near the load, pick a point VOUT that will be the regulation center; run a single unloaded narrow trace from there to the compensation components. The same trace can also be used for VOS divider.
Feedback Compensation
This section highlights the design consideration for a voltagemode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended, as shown in the top part of Figure 13. Figure 13 also highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the ISL6341, ISL6341A, ISL6341B circuit. The output voltage (VOUT) is regulated to the reference voltage, VREF. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) modified saw-tooth wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank's equivalent series resistance is represented by the series resistor E. The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis, L and D represent the channel inductance and its DCR, while C and E represent the total output capacitance and its equivalent series resistance.
1 F LC = --------------------------2 L C 1 F CE = ----------------------2 C E (EQ. 3)
Q1
LO
VOUT
LGATE/OCSET
CO
RETURN
FIGURE 11. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS
Figure 11 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown should be located as close together as possible. Please note that the capacitors CIN and CO may each represent numerous physical capacitors. For best results, locate the ISL6341, ISL6341A, ISL6341B within 1 inch of the MOSFETs, Q1 and Q2 . The circuit traces for the MOSFET gate and source connections from the ISL6341, ISL6341A, ISL6341B must be sized to handle up to 2A peak current. 12
LOAD
CIN
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6. Calculate C2 such that FP1 is placed at FCE.
C2
C1 C 2 = ------------------------------------------------------2 R 2 C 1 F CE - 1
R3 C1 C3
(EQ. 6)
COMP
R2 -
FB E/A + VREF Ro
R1
7. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below fSW (typically, 0.5 to 1.0 times fSW). fSW represents the switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter.
VOUT
OSCILLATOR VIN PWM CIRCUIT VOSC L
R1 R 3 = ------------------f SW ---------- - 1 F LC
1 C 3 = ---------------------------------------------2 R 3 0.7 f SW (EQ. 7)
UGATE HALF-BRIDGE DRIVE
D
PHASE
C E
It is recommended that a mathematical model be used to plot the loop response. Check the loop gain against the error amplifier's open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL):
d MAX V IN 1 + s(f) E C G MOD ( f ) = ----------------------------- ---------------------------------------------------------------------------------------2 V OSC 1 + s(f) (E + D) C + s (f) L C 1 + s(f) 2 1 G FB ( f ) = -------------------------------------------------- R C C s(f) 1 ( 1 + 2) R R C 1 + s(f) ( 1 + 3) 3 ---------------------------------------------------------------------------------------------------------------------- C1 C2 R C R ( 1 + s ( f ) 3 3 ) 1 + s ( f ) 2 ------------------- C1 + C2 G CL ( f ) = G MOD ( f ) G FB ( f ) where, s ( f ) = 2 f j (EQ. 8)
R C
LGATE
ISL6341, ISL6341A, ISL6341B
EXTERNAL CIRCUIT
FIGURE 13. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
The compensation network consists of the error amplifier (internal to the ISL6341, ISL6341A, ISL6341B) and the external R1 to R3, C1 to C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of fSW) and adequate phase margin (better than 45). Phase margin is the difference between the closed loop phase at F0dB and 180. The equations that follow relate the compensation network's poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 13. Use the following guidelines for locating the poles and zeros of the compensation network: 4. Select a value for R1 (1k to 5k, typically). Calculate the value for R2 for desired converter bandwidth (F0). If setting the output voltage via an offset resistor connected to the FB pin (Ro in Figure 13), the design procedure can be followed as presented.
V OSC R 1 F 0 R 2 = -------------------------------------------d MAX V IN F LC (EQ. 4)
COMPENSATION BREAK FREQUENCY EQUATIONS
1 F Z1 = ----------------------------R C 2 2 1 1 F Z2 = ----------------------------------------------R R C 2 ( 1 + 3 ) 3 1 F P1 = ------------------------------------------C C R 1 2 ------------------2 2 C C 1+ 2 1 F P2 = ----------------------------R C 2 3 3
(EQ. 9)
5. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC).
1 C 1 = ---------------------------------------------2 R 2 0.5 F LC (EQ. 5)
Figure 14 shows an asymptotic plot of the DC/DC converter's gain vs frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the loglog graph of Figure 14 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain.
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FZ1 FZ2 GAIN FP1 FP2 MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN
careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
R 2 20 log ------- R 1 0
d MAX V IN 20 log --------------------------------V OSC
GFB GCL
LOG
GMOD LOG FLC FCE F0 FREQUENCY
FIGURE 14. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, fSW. This is just one method to calculate compensation components; there are variations of the compensation break frequency equations. The error amp is similar to that on other Intersil regulators, so existing tools can be used here as well. Special consideration is needed if the size of a ceramic output capacitance in parallel with bulk capacitors gets too large; the calculation needs to model them both separately (attempting to combine two different capacitors types into one composite component model may not work properly; a special tool may be needed; contact your local Intersil person for assistance).
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by Equation 10:
I = VIN - VOUT Fsw x L x VOUT VIN VOUT = I x ESR (EQ. 10)
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6341, ISL6341A, ISL6341B will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. Equation 11 gives the approximate response time interval for application and removal of a transient load:
tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT (EQ. 11)
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be 14
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check Equation 11 at the minimum and maximum output levels for the worst case response time.
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Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2 . The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. Losses while Sourcing Current
2 1 P UPPER = Io x r DS ( ON ) x D + -- Io x V IN x t SW x F S 2 2xr PLOWER = Io DS(ON) x (1 - D)
Losses while Sinking Current
(EQ. 12) 1 P LOWER = Io x r DS ( ON ) x ( 1 - D ) + -- Io x V IN x t SW x F S 2 Where: D is the duty cycle = VOUT / VIN , tSW is the combined switch ON and OFF time, and fSW is the switching frequency.
2
PUPPER = Io2 x rDS(ON) x D
When operating with a 12V power supply for VCC (or down to a minimum supply voltage of 4.5V), a wide variety of N-MOSFETs can be used. Check the absolute maximum VGS rating for both MOSFETs; it needs to be above the highest VCC voltage allowed in the system; that usually means a 20V VGS rating (which typically correlates with a 30V VDS maximum rating). Low threshold transistors (around 1V or below) are not recommended, for the reasons explained in the following paragraph. For 5V only operation, given the reduced available gate bias voltage (5V), logic-level transistors should be used for both N-MOSFETs. Look for rDS(ON) ratings at 4.5V. Caution should be exercised with devices exhibiting very low VGS(ON) characteristics. The shoot-through protection present aboard the ISL6341, ISL6341A, ISL6341B may be circumvented by these MOSFETs if they have large parasitic impedences and/or capacitances that would inhibit the gate of the MOSFET from being discharged below its threshold level before the complementary MOSFET is turned on. Also avoid MOSFETs with excessive switching times; the circuitry is expecting transitions to occur in under 50ns or so.
MOSFET Selection/Considerations
The ISL6341, ISL6341A, ISL6341B requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see Equation 12). Equation 12 assumes linear voltage-current transitions and does not adequately model power loss due to the reverserecovery of the upper and lower MOSFET's body diode. The gate-charge losses are dissipated by the ISL6341, ISL6341A, ISL6341B and don't heat the MOSFETs. However, large gatecharge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
BOOTSTRAP Considerations
Figure 15 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VGD. For convenience, VGD usually shares the VIN or VCC supply; it can be any voltage in the 5V to 12V range. The boot capacitor, CBOOT, develops a floating supply voltage referenced to the PHASE pin. The supply is refreshed to a voltage of VGD less the boot diode drop (VD) each time the lower MOSFET, Q2 , turns on. Check that the voltage rating of the capacitor is above the maximum VCC voltage in the system; a 16V rating should be sufficient for a 12V system. A value of 0.1F is typical for many systems driving single MOSFETs. If VCC is 12V, but VIN is lower (such as 5V), then another option is to connect the BOOT pin to 12V, and remove the BOOT cap (although, you may want to add a local cap from BOOT to GND). This will make the UGATE VGS voltage equal to (12V - 5V = 7V). That should be high enough to drive most MOSFETs, and low enough to improve the efficiency slightly. This also saves a boot diode (and capacitor).
15
FN6538.0 August 20, 2007
ISL6341, ISL6341A, ISL6341B
+VCC VCC +VGD - VD + BOOT CBOOT UGATE PHASE VCC + Q1 VG-S VGD - VD Q2 LGATE/OCSET VG-S VCC +VIN
ISL6341, ISL6341A, ISL6341B
-
GND
FIGURE 15. UPPER GATE DRIVE BOOTSTRAP
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FN6538.0 August 20, 2007
ISL6341, ISL6341A, ISL6341B Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L10.3x3B
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A3 b D 0.18
6 INDEX AREA TOP VIEW B
0.25 3.00 BSC
0.30
5, 8 -
D2 E
// 0.10 C 0.08 C
2.23
2.38 3.00 BSC
2.48
7, 8 -
E2 e k
1.49
1.64 0.50 BSC
1.74
7, 8 -
A C SEATING PLANE SIDE VIEW A3
0.20 0.30
0.40 10 5
0.50
8 2 3 Rev. 0 2/06
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN6538.0 August 20, 2007

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